Test floor is closely linked with ASIC Design process and is optimized for analog performance. We have customized our Automated Test Equipment (ATE) to reduce test lead length from test head to Device Under Test (DUT) by an order of magnitude to what is accepted as a norm on most test floors. This reduces noise and stray pin loading during test. The result is a dramatic increase in speed, repeatability, package yield, and overall test quality.


• Fully automated wafer and package level test
• Fully automated, online Test and QA Procedures
• Mil-Std-105
• 100% wafer level test, each device
• 100% package level test, each package
• Real Time Yield Statistics
• Wafer and Package Level tests correlated
• 100% Datalog, each device
• At Temperature Test